Conventionally, a quarternary phase-shift keying telecommunication system (referred as QPSK system) is widely used in digital telecommunication systems.
In the QPSK system, a carrier wave is phase-modulated by a digital signal, e.g., a pulse code modulation signal (referred as PCM signal hereafter) in the well-known quarternary phase-shift keying QPSK manner at a transmitter. Thus, a QPSK modulation wave is produced in the transmitter. The QPSK modulation wave is transmitted to a receiving station, such as a QPSK system receiver. The QPSK system receiver reproduces the carrier wave from the received QPSK modulation wave. Then, the receiver demodulates the PCM signal from the received QPSK modulation wave by a synchronous demodulation using the reproduced carrier wave.
The reproduction of the carrier wave in the QPSK system receiver is carried out by using a phase locked loop (referred as PLL hereafter) circuit, as is well known.
When such a QPSK demodulation is performed through the synchronous demodulation at the QPSK system receiver in a communication system using a carrier, it is necessary to reproduce a carrier wave in the same standard phase as the carrier wave used in the transmitter.
FIG. 1 is a block diagram showing an example of the QPSK system receiver which performs such a QPSK demodulation for reproducing the carrier wave and for demodulating the PCM signal from the received QPSK modulation wave. In the QPSK system, the QPSK modulation wave carrying the PCM signal is supplied to the QPSK system receiver. The PCM signal has, e.g., two channel digital signals being transmitted via a cable from a transmitter.
In FIG. 1, the QPSK modulation wave is input to an input terminal Pin of the QPSK system receiver. The QPSK modulation wave input to the QPSK system receiver is applied to a tuner 11. The tuner 11 shifts down the high frequency of the QPSK modulation wave, i.e., the RF (radio frequency) signal, to a first prescribed IF (intermediate frequency) signal. A first local oscillator 12a supplies a first local frequency signal with a prescribed variable frequency to the tuner 11. The frequency of the first local frequency signal varies in accordance with a tuning operation so that a desired one of the QPSK modulation waves input to the QPSK system receiver is tuned by the tuner 11. Thus, the tuned QPSK modulation wave, i.e., the RF signal is converted to the first IF signal.
The first IF signal output from the tuner 11 is applied to a frequency converter 13. The frequency converter 13 again shifts down the frequency of the first IF signal to a second prescribed IF signal. A second local oscillator 12b supplies a second local frequency signal with a prescribed fixed frequency to the frequency converter 13. The circuit consisting of the tuner 11, the first and second local oscillators 12a, 12b and the frequency converter 13 forms a well-known double frequency conversion system. Thus, the frequency converter 13 outputs a second IF signal lower in frequency than the first IF signal.
The second IF signal is applied to a first input terminal P1 of a QPSK signal demodulator 14. The QPSK signal demodulator 14 constitutes an integrated circuit comprising a phase comparator section 14a and a synchronous demodulator section 14b.
The phase comparator section 14a compares the phase of the second IF signal which represents the QPSK modulation signal transmitted from the transmitter with a phase signal as described below, which is supplied to a second input terminal P2 of the QPSK signal demodulator 14. Thus, the phase comparator section 14a outputs a phase error signal between the QPSK modulation signal and the phase signal from a first output terminal P3 of the QPSK signal demodulator 14.
The synchronous demodulator section 14b demodulates the PCM signal from the QPSK modulation signal in synchronism with the phase signal.
The QPSK signal demodulator 14 is coupled to a carrier wave reproducing circuit 15. The carrier wave reproducing circuit 15 forms a PLL circuit 16 together with the phase comparator section 14a in the QPSK signal demodulator 14. The carrier wave reproducing circuit 15 comprises a low pass filter (referred as LPF hereafter) 17, a voltage superposing circuit 18 and a voltage controlled oscillator (referred as VCO hereafter) 19.
The phase error signal output from the phase comparator section 14a in the QPSK signal demodulator 14 is applied to the LPF 17. The LPF 17 generates a DC signal having a level variable in correspondence with the phase error signal. The variable DC signal output from the LPF 17 is applied to the voltage superposing circuit 18. The voltage superposing circuit 18 includes therein a voltage source with a fixed voltage. The variable DC signal output from the LPF 17 is superposed on the fixed voltage of the voltage source in the voltage superposing circuit 18. Thus, the voltage superposing circuit 18 supplies a superposed voltage to the VCO 19.
The VCO 19 oscillates under the control of the superposed voltage supplied from the voltage superposing circuit 18. The VCO 19 is designed to oscillate at an oscillation frequency identical with the frequency of the carrier wave used in the transmitter, when only the fixed voltage is supplied from the voltage superposing circuit 18 without the variable DC signal. Thus, the oscillation frequency of the VCO 19 is corrected so that it becomes equal in frequency and phase to the carrier wave, in response to the DC signal output from the LPF 17.
The oscillation output (referred as VCO signal hereafter) of the VCO 19 is fed back to the phase comparator section 14a in the QPSK signal demodulator 14. The PLL circuit 16, comprising the phase comparator section 14a in the QPSK signal demodulator 14 and the carrier wave reproducing circuit 15, automatically stabilizes the phase and the frequency of the VCO signal. As a result, the carrier wave used in the transmitter is reproduced as the VCO signal by the PLL circuit 16, comprising the carrier wave reproducing circuit 15 and the phase comparator section 14a of the QPSK signal demodulator 14.
The carrier wave thus reproduced is supplied to the synchronous demodulator section 14b of the QPSK signal demodulator 14. Then the synchronous demodulator section 14b demodulates the PCM signal from the QPSK modulation wave applied to the input terminal P1 of the QPSK signal demodulator 14 in accordance with the synchronous demodulation under the control of the reproduced carrier wave. The PCM signal thus demodulated is supplied to a PCM decoder 20. The PCM decoder 20 decodes digital signals from the PCM signal. The digital signals are applied to a digital to analog converter (not shown) for converting the digital signals to corresponding analog signals through an output terminal Pout of the QPSK system receiver.
In the conventional QPSK system receiver described above, the VCO 19 utilizes a voltage control type crystal oscillator. The oscillation frequency of the crystal oscillator responding to the fixed voltage is set to a frequency the same as the frequency, e.g., 6.4 MHz, of the carrier wave of the QPSK modulation wave. The PLL circuit 16, comprising the phase comparator section 14a of the QPSK signal demodulator 14 and the carrier wave reproducing circuit 15, operates to minimize the phase error signal output from the phase comparator section 14a of the QPSK signal demodulator 14, i.e., the DC signal output from the LPF 17. Thus, the PLL circuit 16 automatically locks the phase of the reproduced carrier wave into the phase of the QPSK modulation wave.
Conventionally, the PLL circuit 16 is designed to be stable and thus is capable of accurately causing the phase of the reproduced carrier wave to lock with the phase of the QPSK modulation wave. However, if the PLL circuit 16 is designed to be stable, the effective lock range in which the phase error signal is reduced becomes narrow.
The phase error signal corresponds to the difference between phases or frequencies of the QPSK modulation wave and the VCO signal, i.e., the reproduced carrier wave output from the VCO 19. A large amount of the phase error signal occurs, for example, at the instant of power ON, during channel switching or during receipt of a foreign disturbance. Thus, the PLL circuit 16 often goes out of the phase locked state for the QPSK modulation wave, and, into a phase unlocked state. For example, if it is assumed that the QPSK modulation wave has a frequency of 450 MHz, the PLL circuit 16 typically requires a frequency lock range of more than 100 kHz. However, it is difficult to have such a wide frequency lock range and also to establish a satisfactory stability of PLL operation in the PLL circuit 16.
Further, in the conventional QPSK system receiver, it is also difficult to recover the PLL circuit 16 to the phase locked state, if the phase unlocked state has occurred.